One type of flash erasable and electrically programmable read-only memory (flash EPROM") is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of a plurality of memory cells in one row. Each bit line is connected to the drains of a plurality of memory cells in one column. The sources of all the memory cells are connected to their respective common source lines. The prior flash EPROM can be programmed, and once programmed, the entire contents of the prior flash EPROM can be erased by electrical erasure. A high erasing voltage V.sub.PP is made available to the source of all the cells simultaneously. The prior flash EPROM may then be reprogrammed with new data.
The prior flash EPROM typically includes a decoding circuit to address the memory cells. The decoding circuit receives addresses from address input pins of the prior flash EPROM. Data stored in the prior flash EPROM at the applied address can then be mad via data pins of the prior flash EPROM. The prior flash EPROM also typically includes a chip enable pin CE, an output enable pin OE, a power down enable pin PWD, and a write enable pin WE, which are control function pins.
The prior flash EPROM typically includes a plurality of normal operating modes. Those normal operating modes typically include a mad mode, a programming mode, and an erasure mode. For a read mode, a logical low signal is applied to the chip enable pin CE and the output enable pin OE. Data stored in prior flash EPROM are mad out via the data pins as addressed.
A programming mode allows data to be stored by the prior flash EPROM. To enter the programming mode, a logical high signal is applied to the output enable OE pin, a logical low signal is applied to the chip enable CE pin, and a V.sub.PP high voltage is applied to a V.sub.PP pin of the prior flash EPROM. In addition, the programming command is applied to the data pins of the prior flash EPROM prior to the application of the programming data. The write enable signal WE is active low. Once in the programming mode, the data applied to the prior flash EPROM is stored in memory cells of the prior flash EPROM at addresses provided from the address input pins.
The prior flash EPROM enters the erasure mode by writing an erasure command into the prior flash EPROM. The write enable signal WE is active low and the V.sub.PP high voltage is applied to the V.sub.PP pin of the prior flash EPROM. Once in the erasure mode, the prior flash EPROM can undergo either an array erasure operation or a block erasure operation.
The prior flash EPROM enters a standby mode by applying a V.sub.CC voltage at the chip enable pin CE. Power consumption of the prior flash EPROM is substantially reduced in the standby mode. When the PWD pin of the prior flash EPROM receives a logically active low signal, the prior flash EPROM enters a power down mode in which all circuitry of the prior flash EPROM is powered off. Power consumption of the prior flash EPROM is substantially less than that in the standby mode.
One category of the prior flash EPROM has "byte wide" data pins, which comprise 8 bits. Flash EPROMs with byte wide data pins are typically employed in electronic systems that have a byte wide bus for data transfer.
Another category of the prior flash EPROM has "word wide" data pins, which comprises 16 bits. Flash EPROMs with word wide data pins are typically employed in electronic systems that have a word wide bus for data transfer.
One disadvantage associated with the prior byte wide flash EPROM is that a single byte wide flash EPROM typically cannot be used with a word wide bus. Two byte wide flash EPROMs are typically used to satisfy a word wide bus requirement. The disadvantage of using two byte wide memories instead of one is increased printed circuitry board area which translates to higher cost. Also, increased device count typically reduces overall system reliability.
Another disadvantage associated with the prior word wide flash EPROM is that when a prior word wide flash EPROM is used with a byte wide bus, half of the output pins of the prior flash EPROM are left floating. Moreover, only one-half of the storage capacity of the prior word wide flash EPROM is used with the byte wide bus.
One prior solution is to equip a word wide flash EPROM with a word wide and byte wide mode select pin BYTE and a mode select logic. The prior word wide flash EPROM has word wide data pins. When the logical signal applied at the BYTE pin causes the prior word wide flash EPROM to be in the word wide mode, all the data pins of the prior word wide flash EPROM couple data and/or commands to and from the prior flash EPROM. When the logical signal applied at the BYTE pin causes the prior word wide flash EPROM to be in the byte wide mode, the mode select logic disables the buffer coupled to one half of the data pins such that these data pins do not pass data and commands to and from the prior word wide flash EPROM. In addition, the prior word wide flash EPROM receives an extra address signal via one of the disabled data pins. Thus, the prior word wide flash EPROM can be used in both the word wide environment and the byte wide environment.
Disadvantages are, however, associated with this prior approach. One disadvantage associated is that one half of the data pins of the prior word wide flash EPROM are not used in the byte wide mode, which unnecessarily increases the package size of the prior word wide flash EPROM used in the byte wide mode given the extra pins. It is typically desirable to reduce the number of pins of an integrated circuit in order to reduce package size. This would result in smaller printed circuit board layout. Additionally, the reduced pin count would improve system reliability.